1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a data flow control technology in a reconfigurable semiconductor device.
2. Description of the Related Art
A coarse-grained reconfigurable circuit is composed of a plurality of processing elements provided with various functions and an internal-connection network connecting between such processing elements. In the coarse-grained reconfigurable circuit, the functions of the processing elements and a path of the internal-connection network are set in accordance with configuration data, and any function can be realized by changing the configuration data. The coarse-grained reconfigurable circuit is designed such that processing details executed by the processing elements and the path of the data provided to the processing are dynamically reconfigurable in accordance with the configuration data.
The processing element is provided with functions such as computing functions by word unit including four-arithmetic operations and shift and mask operations, a delay processing for adjusting timing, a conditional statement processing like a selector, and a bit processing including logical AND/OR operations. Further, with the above-described functions and so on, the processing element can function as a counter.
The processing performed by stream-oriented applications such as wireless communication and so forth (the processing related to communication stream data) includes a processing with a data flow control processing. Such a processing with the flow control includes a processing that executes a pipeline processing by converting a single input data into sequential series data and also a processing that, on the other hand, retrieves only a single valid data from sequential series data for computation. As an example of the former processing, there is a processing of spreading code (refer to FIG. 8A) in which a 1-bit input (code) is multiplied by a multiple-bits spread code to be converted into a multiple-bits signal. As an example of the later processing, there is a data transfer processing (refer to FIG. 9A and FIG. 9B) between circuits operating at different frequencies, for example, a data transfer processing from a circuit operating at a lower frequency to a circuit operating at a higher frequency.
In order to realize the processing as described above, in the case of a normal circuit of which circuitry is fixed, what should be done is only to install a circuit simply executing the processing in advance. Meanwhile, in the case of the reconfigurable circuit, a processing form like that of a so-called data flow machine is preferable. Hence, in order to realize a processing as described above using a basic function provided in the processing element, many processing elements are required.
For instance, in order to realize a processing of spreading code that uses the multiple-bits (for example, n-bits) spread code as shown in FIG. 8A, a 1-bit input (code) is further repeated (n−1) times for the purpose of repeating the same input (code) in terms of time. By multiplying the input with the n-bits spread code, an n-bits signal after the code-spreading processing is obtained.
Specifically, as shown in FIG. 8B, an input signal is converted into parallel signals by being branched, and after that a selector 103 sequentially selects a signal in accordance with an output from a counter 102 to carry out a parallel-serial conversion process, so that a sequential one-dimensional series signal is obtained. By multiplying the one-dimensional series signal with the spread code thereafter using a logical exclusive OR operator (XOR operator) 104, a desired code after the spread processing can be obtained. Here, in the previous step of the parallel-serial conversion by the selector 103, timing adjustments are performed by delay devices 101-1, 101-2, . . . , 101-(n−1) so that outputs thereof are arranged sequentially.
Each of the delay device 101, counter 102, selector 103 and XOR operator 104 is composed of a single processing unit. Accordingly, in order to realize the processing of spreading code using, for example, an n-bits spread code by the reconfigurable circuit, (n−1) piece(s) of delay device(s) 101 capable of delaying by “n” at maximum, the counter 102, the n-inputs selector 103, the XOR operator 104 are used, requiring many processing elements.
[Patent Document 1] Japanese Patent Application Laid-open No. 2004-199694